S00_AXI
interface pin on the AXI Interconnect to an
external port.An interface is a grouping of signals that share a common function, containing both individual signals and multiple buses. By grouping these signals and buses into an interface, the Vivado IP integrator can identify common interfaces and automatically make multiple connections in a single step. See the Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994) for more information on interface pins and ports.
- Right-click the
S00_AXI
interface pin on the AXI Interconnect to open the pop up menu and select Create Interface Port.
The Create Interface Port dialog box opens, as shown in the following figure.
- Click OK to accept the default
settings.
The Vivado IP integrator adds the external
S00_AXI
interface port to the subsystem design, and automatically connects it to theS00_AXI
interface pin on the AXI Interconnect core.On the AXI Interconnect, connect the Clock and the Reset pin to external ports using the Create Port command. Because these are not interface pins, you do not need an interface port to connect them.
- Right-click the
ACLK
pin of the AXI Interconnect, and select Create Port, as shown in the following figure:
- In the Create Port dialog box, as
shown in the following figure, for Frequency (MHz), enter
200
, and leave the remaining fields set to the default values. - Click OK.
- Right-click the
ARESETN
pin of the AXI Interconnect, and select Create Port.The Create Port dialog box opens as seen in the following figure.
- For Polarity, select Active Low.
- Click OK.
Important: IP integrator treats an external reset coming into the block design as asynchronous to the clocks. You should always synchronize the external resets with a clock domain in the IP subsystem to help the design meet timing.You can use a Processor System Reset block (
proc_sys_reset
) to synchronize the reset. The Processing System Reset is a soft IP that handles numerous reset conditions at its input and generates appropriate system reset signals at its output; however, if a clock and a reset are synchronized external to the block design, you can associate the reset signal with the clock on the external port. You do not need to use the Processor System Reset block in such cases. - Double-click the
ACLK
port to open the Customize Port dialog box. - A clock is typically associated with a Bus Interface. In this case, you can
associate this clock pin to the
S00_AXI
interface. In the Associated Busif field, typeS00_AXI
. - For the Associated Reset field, enter
ARESETN
. - Click OK.The dialog box looks like the following figure:
Now you can connect the AXI clock and reset nets to the remaining master and slave clocks and resets of the AXI Interconnect.
- Place the cursor on top of the
S00_ACLK
pin of the AXI Interconnect.Note: The cursor changes into a pencil indicating that you can make a connection from that pin. Clicking the mouse button here starts a connection on theS00_ACLK
pin. - Click and drag the cursor from the
S00_ACLK
pin to theACLK
port.Tip: You must press and hold down the mouse button while dragging the connection from theS00_ACLK
pin to theACLK
port.As you drag the connection wire, a green checkmark appears on the
ACLK
port indicating that you can make a valid connection between these points. The Vivado IP integrator highlights all possible connection points in the subsystem design as you interactively wire the pins and ports. - Release the mouse button and Vivado IP
integrator makes a connection between the
S00_ACLK
pin and theACLK
port, as shown in the following figure:
- Repeating the steps outlined above, connect the
M00_ACLK
and theM01_ACLK
to theACLK
port.The connections to the AXI Interconnect should now appear as shown in the following figure:
Similarly, connect the reset pins of all the masters and slaves to the
ARESETN
port. - Place the cursor on the
S00_ARESETN
pin, then click and drag the cursor to theARESETN
port as shown below. - Release the mouse button to make the connection.
- Repeat the steps to connect the
M00_ARESETN
and theM01_ARESETN
pins of the AXI Interconnect to theARESETN
port, as shown in the following figure: