Step 5: Running Connection Automation - 2024.1 English

Vivado Design Suite Tutorial: Designing IP Subsystems Using IP Integrator (UG995)

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2024.1 English

At this point, there are still some output interface pins that you must connect external to the subsystem design, such as the following:

  • UART interface of the AXI UART Lite
  • SPI_0 interface of the AXI Quad SPI
  • IIC interface of the AXI IIC
Note: The AXI Block RAM Controller is not connected to a Block Memory Generator.

IP integrator offers the Designer Assistance feature to automate certain kinds of connections. For the current subsystem design, you can connect the UART, SPI, and IIC interfaces to external ports using connection automation. You can also use the Designer Assistance feature to connect a Block Memory Generator to the Block RAM Controller.

  1. Click Run Connection Automation in the banner at the top of the design canvas.

    The Run Connection Automation dialog box opens.

  2. Select All Automation (5 out of 5 selected) as shown in the following figure. This selects all external interfaces and the BRAM Controller for auto connection.

  3. Select and highlight the interfaces, as shown in the following figure, to see a description of the automation that the tool offers, also any options needed to connect these interfaces.

  4. Click OK.
  5. All the external interfaces connect to I/O ports, and the Block RAM Controller connects to the Block Memory Generator, as shown in the following figure:
  6. Right-click the newly added spi_rtl_0 port to open the popup menu and select the External Interface Properties command.

    In the External Interface Properties window, you can change the name of the port if needed. The Vivado IP integrator automatically assigns the name of the port when connection automation is run. For now, leave the spi_rtl_0 port named as it is.

  7. Right-click the ext_spi_clk pin of the AXI Quad SPI, and select Create Port.

    The Create Port dialog box opens as shown in the following figure:

  8. For the Frequency (MHz) field, enter 100, if it is not already set, and click OK.
  9. Click Regenerate Layout button to redraw the subsystem design.

    The optimized layout of the design should now look similar to the figure below: