Introduction - 2023.2 English

Vivado Design Suite Tutorial: Designing IP Subsystems Using IP Integrator (UG995)

Document ID
Release Date
2023.2 English
Important: This tutorial requires the use of the AMD Kintex™ 7 family of devices. You need to update your AMD Vivado™ tools installation if you do not have this device family installed. Refer to the Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973) for more information on Adding Design Tools or Devices.

The AMD Vivado™ Design Suite IP integrator lets you create complex system designs by instantiating and interconnecting IP cores from the Vivado IP catalog onto a design canvas. You can create designs interactively through the IP integrator design canvas GUI, or programmatically using a Tcl programming interface. You typically construct designs at the AXI-interface level for greater productivity; but you can also manipulate designs at the port level for more precise design control.

This tutorial walks you through the steps for building a basic IP subsystem design using the IP integrator. You instantiate a few IPs in the IP integrator and stitch them up to create an IP subsystem design. While working through this tutorial, you are introduced to the IP integrator GUI, run design rule checks (DRC) on your design, and integrate the design into a top-level design in the Vivado Design Suite. Finally, you run synthesis and implementation and generate a bitstream on the design.

Video: You can also view the Designing with Vivado IP Integrator quick take video to learn more about this feature of the Vivado Design Suite.