The General settings enable you to specify the project name, part, target language, target simulator, top module name, and language options.
- Name
- Specifies the project name.
- Project Device
- Specifies the target device to be used as a default for both
synthesis and implementation. Click the browse button to open the
Select Device dialog box to choose
a device.Note: If you have multiple synthesis or implementation runs, you can also change the device used for a specific run by changing the run settings from the Run Properties window. For more information, see the Vivado Design Suite User Guide: Using the Vivado IDE (UG893).
- Target Language
- Specifies the target output language for the design as either Verilog or VHDL. The tool generates RTL output from the design in the specified target language. Specific examples of output controlled by the target language are synthesis, simulation, top-level wrappers, test benches, and IP instantiation templates.
- Default Library
- Specifies the default library for the project. All files without an explicit library specification are compiled in this library. You can select a library name, or specify a new library name by typing in the Library text field.
- Top Module Name
- Specifies the top RTL module name of the design. You can also enter a lower-level module name to experiment with synthesis on a specific module. Click the browse button to automatically search for the top module and display a list of possible top modules.
- Language Options
-
Important: The settings here apply to synthesis. You can also define Verilog options and Generics/Parameters options from the Settings - Simulation dialog box. The simulation settings apply to the simulation fileset and affect simulation but not synthesis.
- Verilog Options
- Click the browse button to set the following options in the Verilog Options dialog box.
- Verilog Include Files Search Paths
- Specifies the paths to search for files referenced by 'include statements in the source Verilog files.
- Defines
- Specifies Verilog macro definitions for the project.
- Uppercase all identifiers
- Sets all Verilog identifiers to uppercase.
- Generics/Parameters
- VHDL supports generics while Verilog supports defining parameters for constant values. Both of these techniques allow parameterized designs that can be reused in different situations. Click the browse button to define generic and parameter values to override defaults defined in the source files.
- Loop Count
- Specifies the maximum loop iteration value. The
default is 1000.Note: The Loop Count option is used during RTL elaboration but does not apply to synthesis. For synthesis, you must specify the -loop_iteration_limit switch in the More Options field of the Synthesis page of the Settings dialog box.
Figure 1. General Settings
