Running Methodology Checks - 2024.1 English

Vivado Design Suite User Guide: System-Level Design Entry (UG895)

Document ID
UG895
Release Date
2024-05-30
Version
2024.1 English

The Vivado Design Suite provides automated methodology checks based on the UltraFast Design Methodology Guide for FPGAs and SoCs (UG949) using the Report Methodology command.

You can generate a methodology report on an opened, elaborated, synthesized, or implemented design. For an elaborated design, the methodology report checks the XDC and RTL files. For information on running the methodology report using Tcl commands, see the Vivado Design Suite Tcl Command Reference Guide (UG835).