Creating a Post-Synthesis Project - 2024.1 English

Vivado Design Suite User Guide: System-Level Design Entry (UG895)

Document ID
UG895
Release Date
2024-05-30
Version
2024.1 English

A post-synthesis project begins with a synthesized netlist, fully generated block designs, fully generated IP, and corresponding constraints. You can then analyze, floorplan, and implement the design.

Note: You can use either XST or third-party synthesis tools to create the synthesized netlist.
Important: When working with EDIF and NGC files, the top cell name must match the name of the file.
  1. Follow the steps in Creating a Project.
  2. In the Project Type page, select Post-Synthesis Project, and click Next.
    Note: If necessary, you can select Do not specify sources at this time. This skips the steps of adding design sources and enables you to select the target part and create the project.
  3. In the Add Netlist Sources page, use the following options to specify netlist files to read, identify the file containing the top module, and define directories to search for lower-level module netlist, and click Next.
    Add Files
    Invokes a file browser so you can select netlist files (structural Verilog, SystemVerilog, EDIF or NGC), BD Files, and XCI files (all the output products for the IP must be generated, including the DCP), or design checkpoint files (DCP) to add to the project.
    Note: Enable the Top radio button for the file that contains the top-level netlist.
    Add Directories
    Invokes a directory browser so you can select directories to search for modules. Files in the specified directory with valid source file extensions are added to the project.
    Remove
    The button removes the selected source files and directories from the list.
    Move Up/Move Down
    Moves the file or directory up/down in the list order. The order of the files affects the processing order.
    Copy Sources into Project
    Copies files into the local project directory instead of referencing the original files. If you added directories of source files using Add Directories, the directory structure is maintained when the files are copied locally into the project. For more information, see Using Remote Sources or Copying Sources into Project.
    Add Sources from Subdirectories
    Looks for netlist files in the subdirectories of directories specified with Add Directories.


  4. Optional: In the Add Constraints page, set the following options, and click Next:
    Add Files
    Invokes a file browser so you can select SDC or XDC files to add to the project.
    Create File
    Creates a new top-level XDC file for the project.
    Remove
    Removes the selected file from the constraint list.
    Move Up/Move Down
    Moves a constraint file up or down in the listed order. Commands are order-dependent; the last-read command of a constraint overwrites the effects of an earlier command.
    Copy Constraints into Project
    Copies constraint files into the local project directory instead of referencing the original files.
    Note: Any SDC or XDC file found in the same directories as the RTL or netlist source files associated with the project are automatically listed as constraint files to be added to the project.
  5. In the Default Part page, select an AMD part or TDP board, and click Next:
    Parts
    Lists available devices. Information about the device resources displays in a table view. You can filter the list using the Product Category, Family, Sub-Family, Package, Speed Grade, and Temp Grade filters. You can also use the Search field to find specific devices.
    Boards
    Lists available TDP boards, and the AMD part used on the board. Information about device resources displays in a table view, such as I/O pin count, the number of LUTs and flip-flops, and available block RAM. You can filter the list using the Vendor, Display Name, and Board Rev filters. You can also use the Search field to find specific board parts.
  6. In the New Project Summary page, view the selected options that define the project, and click Finish.