The JTAG target interface uses a standard 14-pin connector. Xilinx recommends
using the provided 6-inch ribbon cable or 6-inch flying leads to connect the SmartLynq+
Module to the JTAG interface on the target board, as shown in the following figure.
Figure 1. SmartLynq+Module JTAG Connection to the JTAG Interface on a
Target Board
To take advantage of the ribbon cable, a mating connector must be incorporated
into the target board, as is implemented on Xilinx evaluation boards. This connector is
normally installed only during prototype development. When the production hardware is
functional and the JTAG devices can be configured from alternate sources, the connector
can be eliminated from the board cost. Maintaining the footprint for this connector is
recommended if space permits.
The connector has a 2-mm shrouded, keyed header. (See the Header Manufacturers table in GPIO Target Interface for Vendor part numbers.) Mating connectors for
attaching the high-performance ribbon cable to the JTAG port on a target board are
available in both through-hole and surface-mount configurations.
Shrouded and keyed versions should always be used to guarantee proper orientation when
inserting the cable. The connector requires 105 mm2 of board space. The target board
voltage applied to pin 2 of the JTAG connector is used as a power source for the output
buffers that drive the output pins. Target interface connector details including
dimensions, signal assignments, pin descriptions, vendor part numbers, DC electrical and
switching characteristics, and timing are provided in the following tables and figures.
Figure 2. Dimensions and Signal Assignments
Table 1. Interface Pin Descriptions
| Pin Number |
Pin Name |
Direction |
Description |
| 2 |
VREF
|
In |
Target Reference Voltage.
Connected to a voltage bus on the target board that serves the JTAG
interface. |
| 4 |
TMS |
Out |
JTAG Test Mode
Select. JTAG mode signal establishing appropriate
TAP state transitions on all target JTAG devices. |
| 6 |
TCK |
Out |
JTAG Test Clock. Clock signal
for JTAG operations connected to the TCK pin on all target JTAG
devices sharing the same data stream. |
| 8 |
TDO |
In |
JTAG Test Data Out. Serial data
stream received from the TDO pin on the last device in a JTAG
chain. |
| 10 |
TDI |
Out |
JTAG Test Data In. Outputs the
serial data stream transmitted to the TDI pin on the first device in
a JTAG chain. |
| 13 |
PGND |
Out |
JTAG Pseudo Ground. Use of this
pin is optional, if unused it can be left with no connection. PGND
is LOW during JTAG operation. |
| 14 |
SRST |
Out |
System Reset. Use of this pin is optional, if
unused it can be left with no connection. Host applications can
customize the behavior of this signal. |
Table 2. Mating Connectors for 2 mm pitch, 14-Conductor Ribbon Cable
| Manufacturer |
SMT, Vertical |
Through-Hole, Vertical |
Through-Hole, Right Angle |
Website |
| Molex |
87832-1420 |
87831-1420 |
87833-1420 |
www.molex.com |
Table 3. DC Electrical Characteristics
| Symbol |
Description |
Conditions |
Min. |
Max. |
Unit |
| VOH
|
High-level output voltage |
VREF = 1.65V, IOH = –8
mA |
1.2 |
- |
V |
| VREF = 2.3V, IOH = –9
mA |
1.7 |
| VREF = 3V, IOH = –12
mA |
2.3 |
| VOL
|
Low-level output voltage |
IOL = 8 mA |
- |
0.4 |
V |
| IOL = 9 mA |
0.5 |
| IOL = 12 mA |
0.7 |
| VIH
|
High-level input voltage |
VREF = 1.2V to 1.35V |
0.78 |
- |
V |
| VREF = 1.35V to 1.65V |
0.88 |
| VREF = 1.65V to 1.95V |
1.1 |
| VREF = 1.95V to 2.7V |
1.6 |
| VREF = 2.7V to 3.3V |
2 |
| VIL
|
Low-level input voltage |
VREF = 1.2V to 1.95V |
- |
0.4 |
V |
| VREF = 1.95V to 2.7V |
0.7 |
| VREF = 2.7V to 3.3V |
0.8 |
| ICC
|
Dynamic current |
- |
- |
110 |
mA |
Table 4. Switching Characteristics
| Symbol |
Description |
Conditions |
Min. |
Max. |
Unit |
| TCLK
|
Clock period with 50% duty cycle |
50 kHz to 100 MHz |
10 |
8,000 |
ns |
| TCPD
|
Cable Propagation Delay Time (TDI or TMS
relative to the negative edge of TCK) |
VREF
= 1.2V to 3.3V |
- |
1 |
ns |
| TTSU
|
Cable Setup Time (TDO relative to the negative
edge of TCK) |
VREF
= 1.2V to 3.3V |
1 |
- |
ns |
| TCHU
|
Cable Hold Time (TDO relative to the negative
edge of TCK) |
VREF
= 1.2V to 3.3V |
1 |
- |
ns |
Figure 3. SmartLynq+ Module Timing Diagram
