Pre-RTL I/O Planning - 2025.1 English - UG1506

Versal Adaptive SoC Board System Design Methodology Guide (UG1506)

Document ID
UG1506
Release Date
2025-05-29
Version
2025.1 English

Pre-RTL I/O planning is not recommended for Versal devices due to the heavy dependency on AMD IP for memory and other high-speed I/O interfaces, which follow specific rules for clocking.