Corner Banks - 2024.1 English

Versal Adaptive SoC Board System Design Methodology Guide (UG1506)

Document ID
UG1506
Release Date
2024-06-19
Version
2024.1 English

When XPIO banking resources are located adjacent to certain resources such as the processing system (PS) or high-speed transceiver columns, the XPIO bank have limited functionality. Because these restricted XPIO banks are typically located at the corners of a device, they are referred to as corner banks. Corner bank locations vary by device and are explicitly called out in the Versal Adaptive SoC Packaging and Pinouts Architecture Manual (AM013) with a DDRMC designation. Following are considerations when working with corner banks:

  • Although clocking pins (GC) in corner banks have full access to clocking resources, non-clocking pins are restricted to the DDR memory controller functionality. Though usually defined along bank boundaries, in some instances a partial bank on nibble boundaries might be restricted to DDR memory controller use.
  • In pin planning a Versal adaptive SoC design, use corner banks for DDR memory controller interfaces only. When using the Advanced I/O Planner for Advanced I/O Wizard designs, the corner banks are blocked from use.
  • Where GC inputs are used to drive XPIO corner banks, clock buffers BUFGCTRL and BUFGCE_DIV cannot be placed after MMCM because the sites are reserved. The corner bank affected is below the PS (bottom left corner) and does not have full access to programmable logic resources. There is no restriction for the corner bank below the GTs at the bottom right corner.
  • When you need to use an MMCM in the restricted corner bank, the MMCM output clock must go through a BUFGCE to reach any other loads, including BUFGCTRL or BUFGCE_DIV.