DisplayPort Interface

Multimedia User Guide (UG1449)

Document ID
Release Date
1.7 English

The Zynq UltraScale+ MPSoC also includes a hardened DisplayPort (DP) interface module. The DisplayPort interface is located in the PS and can be multiplexed to one of four dedicated high-speed serial transceivers operating at up to 6 Gbps. This eliminates the need for additional display chips to further reduce system BOM cost. The DisplayPort interface is based on the Video Electronics Standards Association (VESA) V-12a specification and provides multiple interfaces to process live audio/video feeds from either the PS or the PL, or stored audio/video from memory frame buffers. It simultaneously supports two audio/video pipelines, providing on-the-fly rendering features like alpha blending, chroma resampling, color space conversion, and audio mixing. This block also includes a dedicated video Phased-Lock Loop (PLL) for generating sync clocks.

Zynq UltraScale+ MPSoC DisplayPort Interface Highlights

  • Up to 4K x 2K video @30 Hz video resolution
  • Y-only, YCbCr444, YCbCr422, YCbCr420, RGB video formats
  • 6, 8, 10, or 12 bits per color components
  • 36-bit native video input interface for live video
  • Captured video interface from frame buffers using built-in DMA
  • Two-plane rendering pipeline
  • Up to two channels of audio, 24-bit at 48 kHz
  • Dedicated video PLL
  • Controller to generate video timing for captured video
  • System time clock (STC) compliant with ISO/IEC 13818-1

For more information on the DP Interface, see Chapter 33: Display Port Controller of the Zynq UltraScale+ Device Technical Reference Manual (UG1085).