Video PHY Controller

Multimedia User Guide (UG1449)

Document ID
Release Date
1.7 English

The AMD Video PHY Controller IP core is designed for enabling plug-and-play connectivity with Video (DisplayPort and HDMI technology) MAC transmit or receive subsystems. The interface between the video MAC and PHY layers is standardized to enable ease of use in accessing shared transceiver resources. The AXI4-Lite interface is provided to enable dynamic accesses of transceiver controls/status.


  • AXI4-Lite support for register accesses
  • Protocol Support for DisplayPort and HDMI
  • Full transceiver dynamic reconfiguration port (DRP) accesses and transceiver functions
  • Independent TX and RX path line rates (device specific)
  • Single quad support
  • Phase-locked loop (PLL) switching support from software
  • Transmit and receiver user clocking
  • Protocol specific functions for HDMI
    • HDMI clock detector
    • Use of fourth GT channel as TX TMDS clock source
    • Non-integer data recovery unit (NI-DRU) support for lower line rates. NI-DRU support is for the HDMI protocol only
  • Advanced clocking support

For more information, see Video PHY Controller LogiCORE IP Product Guide (PG230).