U50 Gen3x16 XDMA base_5 Platform

Alveo Data Center Accelerator Card Platforms User Guide (UG1120)

Document ID
Release Date
2.0.1 English
Platform name
Development name
Supported by
See Table 1 for supported tool versions
Platform UUID
Interface UUID
Release Date
April 2022
Created by
2022.1 tools
Supported XRT versions
2022.1 with support planned through 2023
Satellite controller (SC) FW release
Initial release 5.0.27

For the latest SC FW release notes, see the Alveo U50 Satellite Controller Release Notes 75168.

Link speed
Gen3 x16
Target card

For more information, see Alveo U50 Data Center Accelerator Card.

Release Notes
Change log and known issues for the platform and the SC and CMC firmware are available in the Alveo U50 Master Release Notes Answer Record 75163.

The platform implements the device floorplan shown in the following figure and uses resources across the multiple super logic regions (SLR) of the device. The static and dynamic regions are shown across the SLRs, along with the available HBM memory connections associated with SLR0.

Figure 1. Floorplan

To get the same information for development platforms, after you install the AMD Vitis™ unified software platform, use the platforminfo command utility. It reports information on interfaces, clocks, valid SLRs, allocated resources, and memory in a structured format. For more information, see platforminfo Utility in the Application Acceleration Development flow of the Vitis Unified Software Platform Documentation (UG1416).


The Alveo U50 Data Center accelerator card has 8 GB of high-bandwidth memory (HBM) accessible through 32 pseudo channels. In addition, it is possible to use the device logic resources for small, fast, on-chip memory accesses as PLRAM. The following table lists the allocation of memory resources per SLR.

Note: For details on assigning kernels to HBM memory channels see Mapping Kernel Ports to Memory.
Table 1. Available Memory Resources per SLR
Resources SLR0 SLR1
PLRAM memory channels (system port name) PLRAM[0:1] (128K, block RAM) PLRAM[2:3] (128K, block RAM)
HBM memory channels (system port name) HBM [0:31] (8 GB) No connections


The platform provides a 300 MHz default clock to run the accelerator.

Available Resources After Platform Installation

The following table lists the available resources in the dynamic region of each SLR. It represents the total device resources after subtracting those used by the static region.

Table 2. Platform Resource Availability Per SLR
Resource SLR0 SLR1
CLB LUT 351K 353K
CLB register 703K 707K
Block RAM tile 552 564
UltraRAM 272 272
DSP 2352 2568

Card Thermal and Electrical Protections

The following table lists the power and thermal thresholds for this platform. See CT feature details in Platform Features for how these thresholds are used.

Table 3. Platform Thermal and Electrical Protection Thresholds
Sensor Description Clock Throttling Threshold Clock Shutdown Threshold
3.3V PEX Current 2 3A 3.34A
12V PEX Current 1 5.15A 5.42A
VCCINT temperature 105°C 110°C
FPGA Temperature 92°C 97°C
  1. 12V PEX Current represents power from the PCIe 12V power rail.
  2. 3.3V PEX Current represents power from the PCIe 3.3V power rail.

Deployment Platform Installation

To run applications with this platform, navigate to the Getting Started tab corresponding to your card (see the Alveo Boards and Kits landing page) and download the deployment installation packages and installation guide. Follow the procedures described in the installation guide to install the deployment platform.

Accelerated applications have software dependencies. Work with your accelerated application provider to determine which XRT version to install.

Development Platform Installation

For developing applications for use with the Alveo Data Center accelerator cards you must install and use the Vitis software platform. To set up an accelerator card for use in the development environment, follow the installation steps in: