The core common ports are shown in the following table.
The bridge input interface is compliant with AXI4, and the output interface is compliant with LMB. The input signals Clk and Rst implement clock and
reset for the entire core.
| Port Name | I/O | Clock | Description |
|---|---|---|---|
| Clk | I | AXI and LMB clock | |
| Rst | I | Clk | Reset, active-High |