The AXI LMB Bridge provides configurable FIFO depth for the AXI interface for write address, write data, read address, and read data. The FIFOs allow the AXI interface to transfer address and data in parallel with other ongoing LMB accesses to improve performance.
If the AXI interface is not used simultaneously with other LMB interfaces connected to the local memory (for example, in a use case where it is only active when loading software to the memory), then FIFO depths can be reduced to minimize core resource usage.