LogiCORE™ IP Facts Table | |
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Core Specifics | |
Supported Device Family 1 |
UltraScale+™
Virtex® UltraScale+™ HBM UltraScale™ Zynq®-7000 SoC Zynq® UltraScale+™ MPSoC 7 series Versal® |
Supported User Interfaces | AXI4, LMB |
Resources | Performance and Resource Use web page |
Provided with Core | |
Design Files | Vivado® Register Transfer Level (RTL) |
Example Design | Not Provided |
Test Bench | Not Provided |
Constraints File | Not Provided |
Simulation Model | Not Provided |
Supported S/W Driver | N/A |
Tested Design Flows | |
Design Entry | Vivado® Design Suite |
Simulation | For supported simulators, see the Xilinx Design Tools: Release Notes Guide. |
Synthesis | Vivado Synthesis |
Support | |
Release Notes and Known Issues | Master Answer Record: 000033813 |
All Vivado IP Change Logs | Master Vivado IP Change Logs: 72775 |
Xilinx Support web page | |
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