For full details about performance and resource use, visit the Performance and Resource Use web page.
Latency
The latency is three clock cycles when the AXI interface is idle and LMB is available. Additional latency occurs if LMB is busy handling other interfaces connected to the LMB Block RAM Interface Controller.
Throughput
The AXI interface can sustain one access per clock cycle, provided that the LMB interface is not busy.