TX_CLK_P,TX_CLK_N - 1.0 English

ADC DAC Interface LogiCORE IP Product Guide (PG388)

Document ID
PG388
Release Date
2022-05-16
Version
1.0 English

This differential output denotes the TX CLK generate by XPHY. The frequency of this clock is the same as app_tx_clk. TX_D or {TX_D_P, TX_D_N} are valid only after {TX_CLK_P,TX_CLK_N} starts toggling.