The RX interface signals are externally connected from the ADC to the Versal ACAP. These are described in the following table.
| Port Direction | Port Name | Port Description |
|---|---|---|
| Input | REF_CLK_P, REF_CLK_N | Reference Clock input to XPHY |
| Input | RX_D[M-1:0] | RX Data Input to XPHY for Single Ended IO Designs |
| Input | RX_D_P[M-1:0] | RX Data input to XPHY for Differential IO Designs (P lane of Differential) |
| Input | RX_D_N[M-1:0] | RX Data input to XPHY for Differential IO Designs (N lane of Differential) |