- Pins are divided into three main sections: Data, Strobe, and System Clock.
- Data
- RX_D, TX_D, RX_D_P, RX_D_N, TX_D_P, TX_D_N)
- Strobe
- TX_CLK_P, TX_CLK_N
- System_Clock
- REF_CLK_P, REF_CLK_N
Should fit in maximum of three banks.
- The
app_rstport can be placed beyond the three bank boundary, and only in XP (currently listed as HP in IO planner) banks. - REF_CLK_P and REF_CLK_N pins must be placed only on GCIO pin pairs.
- GCIO pins for clock routing need to be properly selected:
- 1 bank case - The clock should be in the same bank. For example, if the IP is spread across bank 700, REF_CLK_P/N should always be in 700.
- 2 bank case - The clock can be in either of the 2 banks. For example, if the IP is spread across 700 701, REF_CLK_P/N is allowed in either 700 or 701.
- 3 bank case - The clock should always be in middle bank. For example, if 700, 701, 702 is used REF_CLK_P/N should always be in 701.
- Bank-Sharing rules:
- Empty nibbles beyond the extreme ends of the interface can be used by other IP pins.
- Empty pins within an interface nibble can be used only by routethru pins (pins which do not go through the XPHY).
- TX and RX pins must not be placed in the same nibble. A nibble can have either TX pins or RX pins.