Transmitter User Clocking Network Helper Block Ports

The transmitter user clocking network helper block provides a single interface with a source clock input port driven by a transceiver primitive-based output clock. Transmitter user clocking network helper block ports can be identified by the prefix gtwiz_userclk_tx_. For guidance on the usage of the transmitter user clocking network helper block, see Designing with the Core.

The transmitter user clocking network helper block ports described in the following table are present on the Wizard IP core instance when it is configured to locate the transmitter user clocking network helper block in the core.

Table 1. Transmitter User Clocking Network Helper Block Ports
Port Name	I/O	Clock	Description
gtwiz_userclk_tx_reset_in	Input	Async	User signal to reset the clocking resources within the helper block. The active-High assertion should remain until gtwiz_userclk_tx_srcclk_in/out is stable. Width = 1
gtwiz_userclk_tx_srcclk_out	Output	N/A	Transceiver primitive-based clock source used to derive and buffer TXUSRCLK and TXUSRCLK2 outputs. Width = 1
gtwiz_userclk_tx_usrclk_out	Output	N/A	Drives TXUSRCLK of transceiver channel primitives. Derived from `gtwiz_userclk_tx_srcclk_in/out`, buffered and divided as necessary by BUFG_GT primitive. Width = 1
gtwiz_userclk_tx_usrclk2_out			Drives TXUSRCLK2 of transceiver dual primitives. Derived from `gtwiz_userclk_tx_srcclk_in/out`, buffered and divided as necessary by BUFG_GT primitive if required. Width = 1
gtwiz_userclk_tx_active_out		gtwiz_userclk_ tx_usrclk2_out	Active-High indication that the clocking resources within the helper block are not held in reset. Width = 1

The transmitter user clocking network helper block ports described in the following table are present on the core instance when it is configured to locate the transmitter user clocking network helper block in the example design.

Table 2. Transmitter User Clocking Network Helper Block User Interface Ports on Core (Helper Block in Example Design)
Port Name	I/O	Clock	Description
gtwiz_userclk_tx_active_in	Input	Async	When the clocks produced by the transmitter user clocking network helper block are active, this active-High port must be asserted to allow dependent helper blocks within the core to operate. The transmitter user clocking network helper block drives this port by default. Width = 1
gtwiz_userclk_tx_reset_in	Input	Async	It must be driven identically to the gtwiz_userclk_tx_reset_in port on the transmitter user clocking network helper block, present in the example design. Width = 1
gtwiz_userclk_tx_srcclk_in	Input	Async	Transceiver primitive-based clock source used to derive and buffer TXUSRCLK and TXUSRCLK2 outputs. Width = 1

Transmitter User Clocking Network Helper Block Ports - 1.0 English

Virtex UltraScale+ FPGAs GTM Transceivers Wizard LogiCORE IP Product Guide (PG315)