This block implements the transmit and receive transcode and alignment marker, the removal/insertion, and mapping functions for 100G and 50G Ethernet with KP4 FEC. It also implements a simplified transmit alignment lock function like that found in the existing Xilinx® soft RS-FEC IP for 100G and 50G Ethernet. The transcode block supports the latest version of the standards listed in: IEEE Standard for Ethernet (IEEE Std 802.3-2015).
RS-FEC for 100G Ethernet is defined in Clause 91 of IEEE Standard for Ethernet (IEEE Std 802.3-2015). The hard RS-FEC inside the GTM_DUAL supports the RS (544,514) KP4 variant only. The transcoding functions are not included in the hard block, and hence will be implemented in the FPGA logic by this block. A conceptual overview of the RS-FEC datapath in the context of the GTM_DUAL and Transcode helper block is shown in the following figure.
