Reset Controller Helper Block Tie-off Ports - 1.0 English

Virtex UltraScale+ FPGAs GTM Transceivers Wizard LogiCORE IP Product Guide (PG315)

Document ID
PG315
Release Date
2022-05-04
Version
1.0 English

The reset controller helper block ports described in the following table must be tied off. By default, appropriate tie-offs are provided for each core customization.

Table 1. Reset Controller Helper Block Tie-off Ports
Port Name I/O Clock Description
tx_enabled_tie_in Input gtwiz_reset_clk_freerun_in When tied High, transmitter resources are reset as part of the sequence in response to gtwiz_reset_all_in.

Width = 1

rx_enabled_tie_in Input gtwiz_reset_clk_freerun_in When tied High, receiver resources are reset as part of the sequence in response to gtwiz_reset_all_in.

Width = 1

shared_pll_tie_in Input gtwiz_reset_clk_freerun_in When tied High, the shared PLL is reset only once as part of the sequence in response to gtwiz_reset_all_in.

Width = 1