Physical Resources Tab - 1.0 English

Virtex UltraScale+ FPGAs GTM Transceivers Wizard LogiCORE IP Product Guide (PG315)

Document ID
PG315
Release Date
2022-05-04
Version
1.0 English

IP customization options in the Physical Resources tab are described in the following subsections. When customizing options on this tab, it is important to understand that choices you make affect generated HDL and constraints. Select the options that are appropriate for your project and system. For more information, see Virtex UltraScale+ FPGAs GTM Transceivers User Guide (UG581). Users have the option to enable or disable location information in xdc by making the appropriate selection in the Disable Location Information field. The default selection is to not select location information.

Figure 1. Physical Resources Tab
Free-Running and DRP Clock Frequency (MHz)
Specify the frequency of the required free-running clock that will be provided to bring up the core and to clock various helper blocks.
TX Master Channel and RX Master Channel
Independently select the master transmitter and receiver channels from among all enabled transceiver channels. In the generated core instance, the TX master channel drives the source clock input of the transmitter user clocking network helper block, and the RX master channel drives the source clock input of the receiver user clocking network helper block.
Note: These options are unavailable in this release because the clocking helper block is present in the example design, and this can be configured as required.
Number of Duals
This allows you to select the number of duals. Refer to the following table for location specific information. Uncheck the option Disable Location Information, and see the list of available GTM_DUAL locations in the device and select them. Note that the MGT reference clock IBUFDS_GTM is instantiated outside the IP in the Example Design, hence the MGT reference clock selection in GUI is not provided unlike the one's from gtwizard_ultrascale_v1_7 IP. Note that for a few line rates (refer Virtex UltraScale+ FPGAs GTM Transceivers User Guide (UG581)), sharing of MGT reference clock is not allowed, and it is recommended to use local MGT reference clock from same clock region as the GTM_DUAL.
BYPASS_GTM_CNTRL
From 2018.3.1 version of the GTM Wizard IP, a new GTM controller block has been added to enable additional features in future releases. The default GTM Wizard behavior is to enable this block and is not expected to be bypassed.