|
Core Specifics |
| Supported Device Family
1
|
AMD Versal™
Adaptive SoC,
AMD UltraScale+™
Families, 7 series
|
| Supported User Interfaces |
AXI4-Lite, AXI4-Stream
|
| Resources |
Performance and Resource Utilization web
page
|
| Provided with
Core
|
| Design Files |
Not Provided |
| Example Design |
Yes |
| Test Bench |
Not Provided |
| Constraints File |
XDC |
| Simulation Model |
Encrypted RTL, VHDL or Verilog Structural |
| Supported S/W Driver
3
|
Standalone, V4L2 |
| Tested Design
Flows
4
|
| Design Entry |
AMD Vivado™ Design Suite
|
| Simulation |
For supported simulators, see the Vivado Design Suite User Guide: Release Notes,
Installation and Licensing. |
| Synthesis |
Vivado Synthesis |
| Support |
| Release Notes and Known Issues |
Master Answer Record: 68769
|
| All Vivado
IP Change Logs |
Master Vivado IP Change Logs: 72775
|
|
Support web
page
|
- For a complete list of supported devices, see the AMD Vivado™
IP catalog.
- Video protocol as defined in the Video IP: AXI Feature Adoption
section of
Vivado Design Suite: AXI Reference
Guide (UG1037).
- Standalone driver details can be found in the
Vitis directory: <install_directory>/Vitis/<release>/data/embeddedsw/doc/xilinx_drivers_api_toc.htm. Linux Demosaic Driver Page.
- For the supported versions of the tools, see
the Vivado Design Suite User Guide: Release Notes,
Installation and Licensing.
|