The Sensor Demosaic has only one clock domain. All interfaces (master and
slave AXI4-Stream video interfaces and AXI4-Lite interface) use the ap_clk pin as its
clock source.
The pixel throughput of the Sensor Demosaic core is
defined by the product of the clock frequency times the Samples per
Clock setting in the AMD Vivado™
IDE.
With a clock frequency of 300 MHz for ap_clk, and a two sample
per clock configuration, the Sensor Demosaic is capable of a 600 mega pixel throughput rate,
which is sufficient to handle 4K resolutions at 60Hz.