AP_CLK - 1.1 English

Sensor Demosaic LogiCORE IP Product Guide (PG286)

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1.1 English

The AXI4-Stream and AXI4-Lite interfaces must be synchronous to the core clock signal AP_CLK. All AXI4-Stream interface input signals and AXI4-Lite control interface input signals are sampled on the rising edge of AP_CLK. All AXI4-Stream output signal changes occur after the rising edge of AP_CLK.