CSI provides the mobile industry a standard, robust, scalable, low-power, high-speed, cost-effective interface that supports a wide range of imaging solutions for mobile devices.
MIPI CSI-2 TX Controller receives stream of image data via Native video or AXI4-Stream input interface. The controller adds the synchronization packets and performs the pixel-to-byte conversions for the pixel data. Packed byte data is sent over the D-PHY interface for transmission. AXI4-Lite interface is used to access core registers. The MIPI CSI2-TX Controller supports ECC and CRC generation for header and payload, respectively.
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X-Ref Target - Figure 1-2 
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Features of this core include:
• Multi-lane interoperability that allows more bandwidth than that provided by one lane. Those trying to avoid high clock rates, can expand the data path to multiple lanes and obtain approximately linear increases in peak bus bandwidth.
• Short and long packets with all word count values supported and can be used for low level protocol communication.
• Error correction code (ECC) for error generation in Long and Short packet header. To detect possible errors in transmission, a checksum is calculated over each data packet. The checksum is realized as 16-bit CRC. The generator polynomial is x16+x12+x5+x0.
• Supports embedded non-image data transmission using the same input Native video or AXI4S interface.
• Supports active lane configuration, programmable native video interface or AXI4 streaming interface, and programmable CRC generation.
• Supports periodic skew pattern generation for line rates >1.5 Gbps.