Interrupt Status Register (Offset - 0x024)

Interrupt Status Register (Offset - 0x024) - 2.2 English

MIPI CSI-2 Transmitter Subsystem (PG260)

Document ID

PG260

Release Date

2023-05-16

Version

2.2 English

The Interrupt Status register (ISR) is described in Table: Interrupt Status Register and captures the error and status information for the core.

Table 2-16: Interrupt Status Register
Bits	Name	Reset Value	Access ⁽¹⁾	Description
31-16	Reserved	N/A	N/A	Reserved
15-14	Line Count status for VC3	0x0	R/W1C	0x0 - No Error 0x1 - Less number of lines received with respect to lines configured in register 0x4C 0x2 - More number of lines received with respect to lines configured in register 0x4C 0x3 - Reserved
13-12	Line Count Status for VC2	0x0	R/W1C	0x0 - No Error 0x1 - Less number of lines received with respect to lines configured in register 0x48 0x2 - More number of lines received with respect to lines configured in register 0x48 0x3 - Reserved
11-10	Line Count Status for VC1	0x0	R/W1C	0x0 - No Error 0x1 - Less number of lines received with respect to lines configured in register 0x44 0x2 - More number of lines received with respect to lines configured in register 0x44 0x3 - Reserved
9-8	Line Count Status for VC0	0x0	R/W1C	0x0 - No Error 0x1 - Less number of lines received with respect to lines configured in register 0x40 0x2 - More number of lines received with respect to lines configured in register 0x40 0x3 - Reserved
7-6	Reserved	N/A	N/A	Reserved
5	Incorrect Lane Configuration	0x0	R/W1C	Asserted when the Active Lanes is greater than the maximum lanes in the protocol configuration register
4	Generic Short Packet (GSP) FIFO Full	0x0	R/W1C	Asserted when the Generic Short Packet FIFO is full
3	ULPS state	0x0	R/W1C	0: Indicates that the D-PHY lanes have exited the ULPS state or are not in the ULPS state 1: Indicates that the D-PHY lanes are in the ULPS state
2	Line Buffer Full	0x0	R/W1C	Asserted when the Line Buffer is Full
1	Unsupported/Reserved Data Type	0x0	R/W1C	Asserted when the unsupported or the reserved data types are seen in the generic short packet request
0	Pixel Data Under-run	0x0	R/W1C	Asserted when the core starves for pixel data during the packet transmission
Notes: 1. W1C = Write 1 to clear. 2. The bit position from [15:8] is enabled only when the "C_EN_REG_BASED_FE_GEN" parameter is enabled, else the bit position will be reserved.