The MIPI standard serial I/O ports should use MIPI_DPHY_DCI for the I/O standard in the XDC file for UltraScale+ family. The LOC and I/O standards must be specified in the XDC file for all input and output ports of the design. The MIPI CSI-2 TX Subsystem MIPI D-PHY sub-core generates the I/O pin LOC for the pins that are selected during IP customization for UltraScale+ designs. No I/O pin LOC are provided for 7 series MIPI D-PHY IP designs. Restrict the I/O selection within the I/O bank for MIPI D-PHY TX.
You cannot mix MIPI D-PHY TX (or MIPI CSI-2 TX Subsystem) with lane-rate (>1500 Mbps and <=1500 Mbps) in the same HP IO bank.
It is recommended to select the I/O bank with VRP pin connected for UltraScale+ MIPI D-PHY TX IP core. If VRP pin is present in other I/O bank in the same I/O column of the device the following DCI_CASCADE XDC constraint should be used. For example, I/O bank 65 has a VPR pin and the D-PHY TX IP is using the I/O bank 66.
set_property DCI_CASCADE {66} [get_iobanks 65]