The subsystem fits into a image sensor pipe transmission path. The input to the subsystem must be connected to an AXI4-Stream source or Native stream source which generates the pixel data. The output of the subsystem is a MIPI complaint serial data. Because the MIPI protocol does not allow throttling on the output interface (PPI), the module connected to the output of this subsystem should have sufficient bandwidth for the data generated by the image sensor.
Note: When there are multiple instances of MIPI interfaces initialize all interfaces in the same HP IO Bank at the same time. For more information on implementing multiple interfaces in the same HP IO Bank, see UltraScale Architecture SelectIO Resources User Guide ( UG571 ) [Ref 15] .
The Protocol Configuration Register [1:0] can be used to dynamically configure the active lanes used by the subsystem using the following guidelines:
1. Program the required lanes in the Protocol Configuration register only when the following conditions are met:
a. “Enable Active Lanes” is set in the AMD Vivado ™ IDE
b. There is no ongoing transfer on the PPI and all the data lanes are in the stop-state
c. Disable the core.
2. Do not send the new updated lanes traffic until the read from Protocol Configuration registers reflects the new value.
3. After the register read matches the configured value, enable the core and start the image traffic.