• Implementation Details:
° Implementation : This field displays the currently selected architecture. This is useful to see the result of automatic architecture selection.
° Transform Size : When the transform length is run time configurable, the core has the ability to reprogram the point size while the core is running; that is, the core can support the selected point size and any smaller point size. This field displays the supported point sizes based on the Transform Length, Transform Length Options, and the Implementation Options selected.
° Output Data Width : The output data width equals the input data width for scaled arithmetic and block floating-point arithmetic. With unscaled arithmetic, the output data width equals (input data width + log 2 (point size) + 1).
° Resource Estimates : Based on the options selected, this field displays the DSP slice count and 18K block RAM numbers. The resource numbers are just an estimate. For exact resource usage and slice/LUT-FlipFlop pair information, a post-implementation utilization report should be consulted.
° AXI4-Stream Port Structure: This section shows how the FFT fields are mapped to the AXI channels.
• Latency:
° This tab shows the latency of the FFT core in clock cycles and microseconds ( m s) for each point size supported. The latency is from the Upstream Master supplying the first sample of a frame to the last sample of output data coming out of the core, assuming that the FFT core was idle and neither the Upstream Master or the Downstream Slave inserted wait states. This is not the minimum number of cycles between starting consecutive frames, as frames might overlap in some cases. The latency in microseconds is based on the target clock frequency.