| AMD LogiCORE™ IP Facts Table | |
|---|---|
| Core Specifics | |
| Supported Device Family 1 |
AMD Versal™
Adaptive SoC AMD UltraScale+™ AMD UltraScale™ AMD Zynq™ 7000 SoC 7 series |
| Supported User Interfaces | AXI4-Stream |
| Resources | Performance and Resource Utilization web page |
| Provided with Core | |
| Design Files | Encrypted RTL |
| Example Design | Not provided |
| Test Bench | VHDL |
| Constraints File | Not Provided |
| Simulation Model |
Encrypted VHDL C Model |
| Supported S/W Driver | N/A |
| Tested Design Flows 2 | |
| Design Entry |
AMD Vivado™ Design Suite
Vitis Model Composer |
| Simulation | Supported simulators are as follows: Mentor Graphics ModelSim DE (2024.1) Mentor Graphics Questa Advanced Simulator (2024.1) Synopsys VCS (V-2023.12-SP1) |
| Synthesis | Vivado Synthesis |
| Support | |
| Release Notes and Known Issues | Master Answer Record: 54501 |
| All Vivado IP Change Logs | Master Vivado IP Change Logs: 72775 |
| Support web page | |
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