The following table lists the ports that apply to all protocols.
Signal Name | Direction | Default | Width | Description |
---|---|---|---|---|
aclk | Input | Required | 1 |
Interface clock input. Used by both the AXI PC Monitor interface, and the optional AXI4-Lite Control register slave interface. |
aresetn | Input | Required | 1 |
Interface reset input (active-Low). Resets both the AXI PC Monitor interface and the optional AXI4-Lite Control register slave interface. |
system_resetn | Input | Optional | 1 | System reset (active-Low). |
pc_status | Output | 160 | Active-High vector of protocol violations or warnings. | |
pc_asserted | Output | 1 | Active-High signal is asserted when any bit of the pc_status vector is asserted. |