- Supports checking for AXI3, AXI4 and AXI4-Lite protocols
- Interface data widths:
- AXI4 and AXI3: 32, 64, 128, 256, 512, or 1024 bits
- AXI4-Lite: 32 or 64 bits
- Address width: Up to 64 bits
- USER width: Up to 1024 bits (per channel)
- ID width: Up to 32 bits
- Programmable messaging levels for simulation operation
- Supports monitoring of multiple outstanding READ and WRITE transactions
- Instrumented to support AMD Vivado™ Design Suite Debug Nets and connections to Vivado Logic Analyzer monitoring
- AXI4-Lite control register slave interface to read protocol check status