The following table lists AMD-specific checks for configuration-dependent signaling requirements and recommendations.
| Name of Protocol Check | Bit | Notes | Protocol Support | Description |
|---|---|---|---|---|
| XILINX_AW_SUPPORTS_NARROW_BURST | 86 | - | AXI4/AXI3 | When the connection does not support narrow transfers, the AW Master cannot issue a transfer with AWLEN > 0 and AWSIZE is less than the defined interface DATA_WIDTH. |
| XILINX_AR_SUPPORTS_NARROW_BURST | 87 | - | AXI4/AXI3 | When the connection does not support narrow transfers, the AR Master cannot issue a transfer with ARLEN > 0 and ARSIZE is less than the defined interface DATA_WIDTH. |
| XILINX_AW_SUPPORTS_NARROW_CACHE | 88 | - | AXI4/AXI3 | When the connection does not support narrow transfers, the AW Master cannot issue a transfer with AWLEN > 0 and AWCACHE modifiable bit is not asserted. |
| XILINX_AR_SUPPORTS_NARROW_CACHE | 89 | - | AXI4/AXI3 | When the connection does not support narrow transfers, the AR Master cannot issue a transfer with ARLEN > 0 and ARCACHE modifiable bit is not asserted. |
| XILINX_AW_MAX_BURST | 90 | - | AXI4/AXI3 | AW Master cannot issue AWLEN greater than the configured maximum burst length. |
| XILINX_AR_MAX_BURST | 91 | - | AXI4/AXI3 | AR Master cannot issue ARLEN greater than the configured maximum burst length. |
| XILINX_AWREADY_RESET | 92 | - | AXI4/AXI3/Lite |
AWREADY is Low for the first cycle after ARESETn goes High. Xilinx recommends that slaves drive all READY outputs low during reset to avoid dropping a transfer in case the connected master recovers from reset during an earlier cycle. |
| XILINX_WREADY_RESET | 93 | - | AXI4/AXI3/Lite |
WREADY is Low for the first cycle after ARESETn goes High. Xilinx recommends that slaves drive all READY outputs low during reset to avoid dropping a transfer in case the connected master recovers from reset during an earlier cycle. |
| XILINX_BREADY_RESET | 94 | - | AXI4/AXI3/Lite |
BREADY is Low for the first cycle after ARESETn goes High. Xilinx recommends that masters drive all READY outputs low during reset. |
| XILINX_ARREADY_RESET | 95 | - | AXI4/AXI3/Lite |
ARREADY is Low for the first cycle after ARESETn goes High. Xilinx recommends that slaves drive all READY outputs low during reset to avoid dropping a transfer in case the connected master recovers from reset during an earlier cycle. |
| XILINX_RREADY_RESET | 96 | - | AXI4/AXI3/Lite |
RREADY is Low for the first cycle after ARESETn goes High. Xilinx recommends that masters drive all READY outputs low during reset. |
| XILINX_RECS_CONTINUOUS_RTRANSFERS_MAX_WAIT | 97 | L 1 | AXI4/AXI3/Lite | RVALID should be asserted within MAX_CONTINUOUS_RTRANSFERS_WAITS cycles of either the AR command transfer or the previous R transfer while there are outstanding AR commands. |
| XILINX_RECM_CONTINUOUS_WTRANSFERS_MAX_WAIT | 98 | L 1 | AXI4/AXI3/Lite | WVALID should be asserted within MAX_CONTINUOUS_WTRANSFERS_WAITS cycles of either the AW command transfer or previous W transfer while there are outstanding AW commands. |
| XILINX_RECM_WLAST_TO_AWVALID_MAX_WAIT | 99 | L 1 | AXI4/AXI3/Lite | AWVALID should be asserted within MAX_WLAST_TO_AWVALID_WAITS cycles of a WLAST transfer (or AXI4-Lite W transfer) or previous AW transfer if there are yet more WLAST transfers outstanding. |
| XILINX_RECS_WRITE_TO_BVALID_MAX_WAIT | 100 | L 1 | AXI4/AXI3/Lite | BVALID should be asserted within MAX_WRITE_TO_BVALID_WAITS cycles of an AW command transfer or WLAST transfer (or AXI4-Lite W transfer), whichever is later, or previous B transfer if there are yet more completed AW and WLAST transfers outstanding. |
| XILINX_ARESETN_PULSE_WIDTH | 101 | AXI4/AXI3/Lite | ARESETn must be low for at least 16 ACLKn cycles. | |
| XILINX_AXI4_ERRM_NO_STRB_ADDRESS | 102 | L 1 | AXI4/AXI3/Lite | When there is no WSTRB, address must be aligned with the data width |
| XILINX_AXI4_ERRM_SUPPORTS_NARROW_BURST_SIZE | 103 | L 1 | AXI4/AXI3/Lite | When there is support narrow burst along with WSTRB, then AWSIZE has to be greater than or equal to data width |
| XILINX_AXI4_RD_RESP_SLVERR | 104 | - | AXI4/AXI3/Lite | When CHK_ERR_RESP is enabled, this check detects the SLVERR on Read Response |
| XILINX_AXI4_RD_RESP_DECERR | 105 | - | AXI4/AXI3/Lite | When CHK_ERR_RESP is enabled, this check detects the DECERR on Read Response |
| XILINX_AXI4_WR_RESP_SLVERR | 106 | - | AXI4/AXI3/Lite | When CHK_ERR_RESP is enabled, this check detects the SLVERR on Write Response channel |
| XILINX_AXI4_WR_RESP_DECERR | 107 | - | AXI4/AXI3/Lite | When CHK_ERR_RESP is enabled, this check detects the DECERR on Write Response channel |
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