Monitor Port Descriptions for AXI4-Lite Protocol - 2.0 English

AXI Protocol Checker LogiCORE IP Product Guide (PG101)
Document ID
PG101
Release Date
2023-06-21
Version
2.0 English

The following table lists the interface signals for the AXI Protocol Checker monitor interface when it is configured to check an AXI4-Lite Interface.

Table 1. AXI4-Lite Protocol Port Descriptions
Signal Name Direction Default Width Description
pc_axi_awaddr Input Required ADDR_WIDTH Write Address Channel Transaction Address (12-64)
pc_axi_awprot Input 0b000 3 Write Address Channel Protection Characteristics
pc_axi_awvalid Input Required 1 Write Address Channel Valid
pc_axi_awready Input Required 1 Write Address Channel Ready
pc_axi_araddr Input Required ADDR_WIDTH Read Address Channel Transaction Address (12-64)
pc_axi_arprot Input 0b000 3 Read Address Channel Protection Characteristics
pc_axi_arvalid Input Required 1 Read Address Channel Valid
pc_axi_arready Input Required 1 Read Address Channel Ready
pc_axi_wdata Input DATA_WIDTH Write Data Channel Data
pc_axi_wstrb Input All Ones DATA_WIDTH/8 Write Data Channel Byte Strobes
pc_axi_wvalid Input Required 1 Write Data Channel Valid
pc_axi_wready Input Required 1 Write Data Channel Ready
pc_axi_rdata Input DATA_WIDTH Read Data Channel Data
pc_axi_rresp Input 0b00 2 Read Data Channel Response code (0-3)
pc_axi_rvalid Input Required 1 Read Data Channel Valid
pc_axi_rready Input Required 1 Read Data Channel Ready
pc_axi_bresp Input 0b00 2 Write Response Channel Response Code (0-3)
pc_axi_bvalid Input Required 1 Write Response Channel Valid
pc_axi_bready Input Required 1 Write Response Channel Ready