The GT Selection and Configuration tab enables you to configure the serial transceiver features of the core.
Figure 1. GT Selection and Configuration Tab for UltraScale/UltraScale+
Figure 2. GT Selection and Configuration Tab for Versal Adaptive SoC
Option | Values | Default |
---|---|---|
GT Location | ||
Select whether the GT IP is included in the core or in the example design | Include GT subcore in core Include GT subcore in example design |
Include GT subcore in core |
GT Clocks 3 | ||
GT RefClk (In MHz) 1 | 161.1328125 | 161.1328125 |
195.3125 | ||
201.4160156 | ||
257.8125 | ||
322.265625 | ||
312.5 | ||
156.25 | ||
GT DRP Clock (In MHz) | 10.00 - 250.00 MHz | 100.00 |
Core to Transceiver Association | ||
GT Type | GTH, GTY, and GTM, GTYP | GTY |
GT Selection | Options based on device/package quad groups. For example: Quad X0Y1 Quad X0Y2 Quad X0Y3 GTM_DUAL_X0Y0 If the GT type is selected as GTM, the GTM Dual List is available for the selection. For example: GTM_DUAL_X0Y0 GTM_DUAL_X0Y1 |
Quad X0Y0 |
Lane-00 to Lane-03 | Auto filled based on device/package. For example, if Speed = 50G and Num of Cores = 2 (or Speed = 40G and Num of Cores = 1) and GT selection = Quad X0Y1, the four GT lanes are: X0Y4 X0Y5 X0Y6 X0Y7 |
|
RX Equalization Mode | Auto LPM DFE | Auto |
RX Insertion Loss at Nyquist (dB) | Depends on the GT Wizard | 30 |
Others | ||
Enable Pipeline Register | 0, 1 | 0 |
Enable Additional GT Control and Status Ports | 0, 1 | 0 |
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