This is a clear on write register. This is available when the Include ANLT Logic option selected in the Configuration tab.
Bits | Default | Type | Signal |
---|---|---|---|
1:0 | 0 | RW | rx_serdes_reset |
28 | 0 | RW | ctl_an_reset |
29 | 0 | RW | tx_serdes_reset |
30 | 0 | RW | rx_reset |
31 | 0 | RW | tx_reset |