| Name | Size | I/O | Description |
|---|---|---|---|
| gtwiz_loopback_* | 3 | O | GT loopback output signal from AXI4-Lite register map. See the appropriate GT user
guide. This port is available when the Include GT subcore in example design option is selected in the GT Selection and Configuration tab and the AXI4-Lite interface is selected from configuration tab. Note: You need to manually connect this
signal in the bd design.
|
| gtwiz_tx_rate_* | 8 | O | GT TX line rate select from the AXI4-Lite register map. See the appropriate GT user
guide. This port is available when the Include GT subcore in example design option is selected in the GT Selection and Configuration tab and the AXI4-Lite interface is selected from the Configuration tab. |
| gtwiz_rx_rate_* | 8 | O | GT TX line rate selected from the AXI4-Lite register map. See the appropriate GT user
guide. This port is available when the Include GT subcore in example design option is selected in the GT Selection and Configuration tab and the AXI4-Lite interface is selected from Configuration tab. |
| tx_serdes_data_core0_lane0_out | 128 | O | For GT type not equal to GTM, this is the TX data output signal from core to GT of Lane0 (valid bits are lower 64 bits in case of 50G and lower 32-bit in case of 40G speed). |
| tx_serdes_data_core0_lane1_out | 128 | O | For GT type not equal to GTM, this is the TX data output signal from core to GT of Lane1 (valid bits are lower 64 bits in case of 50G and 32-bit in case of 40G speed). |
| tx_serdes_data_core0_lane2_out | 128 | O | For GT type not equal to GTM, this is the TX data output signal from
core to GT of Lane2 (valid bits are lower 32-bit in case of 40G
speed). This port is available only if core speed is 40G or Runtime Switchable option is selected in the Configuration tab. |
| tx_serdes_data_core0_lane3_out | 128 | O | For GT type not equal to GTM, this is the TX data output signal from
core to GT of Lane3 (valid bits are lower 32 bit in case of 40G
speed). This port is available only if core speed is 40G or Runtime Switchable option is selected in the Configuration tab. |
| tx_serdes_header_core0_lane0_out | 6 | O | For GT type not equal to GTM, this is the TX header output signal from core to GT of Lane0 |
| tx_serdes_header_core0_lane1_out | 6 | O | For GT type not equal to GTM, this is the TX header output signal from core to GT of Lane1 |
| tx_serdes_header_core0_lane2_out | 6 | O | For GT type not equal to GTM, this is the TX header outputsignal from
core to GT of Lane2. This port is available only if core speed is 40G or Runtime Switchable option is selected in the Configuration tab. |
| tx_serdes_header_core0_lane3_out | 6 | O | For GT type not equal to GTM, this is the TX header outputsignal from
core to GT of Lane3. This port is available only if the core speed is 40G or Runtime Switchable option is selected in the Configuration tab. |
| rx_serdes_data_core0_lane0_in | 128 | I | For GT type not equal to GTM, this is the RX data input signal from GT to core of Lane0 (valid bits are lower 64 bits in case of 50G and lower 32-bit in case of 40G speed). |
| rx_serdes_data_core0_lane1_in | 128 | I | For GT type not equal to GTM, this is the RX data input signal from GT to core of Lane1 (valid bits are lower 64 bits in case of 50G and lower 32-bit in case of 40G speed). |
| rx_serdes_data_core0_lane2_in | 128 | I | For GT type not equal to GTM, this is the RX data input signal from
GT to core of Lane2. This port is available only if the core speed is 40G or Runtime Switchable option is selected in the Configuration tab. |
| rx_serdes_data_core0_lane3_in | 128 | I | For GT type not equal to GTM, this is the RX data input signal from
GT to core of Lane3. This port is available only if the core speed is 40G or Runtime Switchable option is selected in the Configuration tab. |
| rx_serdes_header_core0_lane0_in | 6 | I | For GT type not equal to GTM, this is the RX header input signal from GT to core of Lane0. |
| rx_serdes_header_core0_lane1_in | 6 | I | For GT type not equal to GTM, this is the RX header input signal from GT to core of Lane1. |
| rx_serdes_header_core0_lane2_in | 6 | I | For GT type not equal to GTM, this is the RX header input signal from
GT to core of Lane2. This port is available only if the core speed is 40G or Runtime Switchable option is selected in the Configuration tab. |
| rx_serdes_header_core0_lane3_in | 6 | I | For GT type not equal to GTM, this is the RX header input signal from
GT to core of Lane3. This port is available only if the core speed is 40G or Runtime Switchable option selected in the Configuration tab. |
| tx_serdes_seq_core0_lane0_out | 6 | O | For GT type not equal to GTM, this is the TX sequence output signal from core to GT of Lane0. |
| tx_serdes_seq_core0_lane1_out | 6 | O | For GT type not equal to GTM, this is the TX sequence output signal from core to GT of Lane1. |
| tx_serdes_seq_core0_lane2_out | 6 | O | For GT type not equal to GTM, this is the TX sequence output signal
from core to GT of Lane2. This port is available only if the core speed is 40G or Runtime Switchable option is selected in the Configuration tab. |
| tx_serdes_seq_core0_lane3_out | 6 | O | For GT type not equal to GTM, this is the TX sequence output signal
from core to GT of Lane3. This port is available only if the core speed is 40G or Runtime Switchable option is selected in the Configuration tab. |
| rx_serdes_headervalid_core0_lane0 | 2 | I | For GT type not equal to GTM, this is the RX header valid input signal from GT to core of Lane0. |
| rx_serdes_headervalid_core0_lane1 | 2 | I | For GT type not equal to GTM, this is the RX header valid input signal from GT to core of Lane1. |
| rx_serdes_headervalid_core0_lane2 | 2 | I | For GT type not equal to GTM, this is the RX header valid input
signal from GT to core of Lane2. This port is available only if the core speed is 40G or Runtime Switchable option is selected in the Configuration tab. |
| rx_serdes_headervalid_core0_lane3 | 2 | I | For GT type not equal to GTM, this is the RX header valid input
signal from GT to core of Lane3. This port is available only if the core speed is 40G or Runtime Switchable option is selected in the Configuration tab. |
| rx_serdes_datavalid_core0_lane0 | 2 | I | For GT type not equal to GTM, this is the RX data valid input signal from GT to core of Lane0. |
| rx_serdes_datavalid_core0_lane1 | 2 | I | For GT type not equal to GTM, this is the RX data valid input signal from GT to core of Lane1. |
| rx_serdes_datavalid_core0_lane2 | 2 | I | For GT type not equal to GTM, this is the RX data valid input signal
from GT to core of Lane2. This port is available only if the core speed is 40G or Runtime Switchable option is selected in the Configuration tab. |
| rx_serdes_datavalid_core0_lane3 | 2 | I | For GT type not equal to GTM, this is the RX data valid input signal
from GT to core of Lane3. This port is available only if the core speed is 40G or Runtime Switchable option is selected in the Configuration tab. |
| rx_serdes_bitslip_core0_lane0 | 1 | O | For GT type not equal to GTM, this is the RX gearbox output signal from core to GT of Lane0. |
| rx_serdes_bitslip_core0_lane1 | 1 | O | For GT type not equal to GTM, this is the RX gearbox output signal from core to GT of Lane1. |
| rx_serdes_bitslip_core0_lane2 | 1 | O | For GT type not equal to GTM, this is the RX gearbox output signal
from core to GT of Lane2. This port is available only if core speed is 40G or Runtime Switchable option is selected in the Configuration tab. |
| rx_serdes_bitslip_core0_lane3 | 1 | O | For GT type not equal to GTM, this is the RX gearbox output signal
from core to GT of Lane3. This port is available only if the core speed is 40G or Runtime Switchable option is selected in the Configuration tab. |
| mst_tx_resetdone_0 | 1 | I | TX master resetdone signal from GT
to core indicates lane0 status. |
| mst_rx_resetdone_0 | 1 | I | RX master resetdone signal from GT
to core indicates lane0 status. |
| mst_tx_resetdone_1 | 1 | I | TX master resetdone signal from GT
to core indicates lane1 status. |
| mst_rx_resetdone_1 | 1 | I | RX master resetdone signal from GT
to core indicates lane1 status. |
| mst_tx_resetdone_2 | 1 | I | TX master resetdone signal from GT
to core indicates lane2 status.This port is available only if the core speed is 40G or Runtime Switchable option is selected in the Configuration tab. |
| mst_rx_resetdone_2 | 1 | I | RX master resetdone signal from GT
to core indicates lane2 status.This port is available only if core speed is 40G or Runtime Switchable option is selected in the Configuration tab. |
| mst_tx_resetdone_3 | 1 | I | TX master resetdone signal from GT
to core indicates lane3 status.This port is available only if cores peed is 40G or Runtime Switchable option is selected in the Configuration tab. |
| mst_rx_resetdone_3 | 1 | I | RX master resetdone signal from GT
to core indicates lane3 status.This port is available only if core speed is 40G or Runtime Switchable option is selected in the Configuration tab. |
| tx_pma_resetdone_0 | 1 | I | TX PMA resetdone signal from GT to
core indicates lane0 status. |
| rx_pma_resetdone_0 | 1 | I | RX PMA resetdone signal from GT to
core indicates lane0 status. |
| tx_pma_resetdone_1 | 1 | I | TX PMA resetdone signal from GT to
core indicates lane1 status. |
| rx_pma_resetdone_1 | 1 | I | RX PMA resetdone signal from GT to
core indicates lane1 status. |
| tx_pma_resetdone_2 | 1 | I | TX PMA resetdone signal from GT to
core indicates lane2 status.This port is available only if the core speed is 40G or Runtime Switchable option is selected in the Configuration tab. |
| rx_pma_resetdone_2 | 1 | I | RX PMA resetdone signal from GT to
core indicates lane2 status. This port is available only if core speed is 40G or Runtime Switchable option is selected in the Configuration tab. |
| tx_pma_resetdone_3 | 1 | I | TX PMA resetdone signal from GT to
core indicates lane3 status. This port is available only if the core speed is 40G or Runtime Switchable option is selected in the Configuration tab. |
| rx_pma_resetdone_3 | 1 | I | RX PMA resetdone signal from GT to
core indicates lane3 status. This port is available only if the core speed is 40G or Runtime Switchable option is selected in the Configuration tab. |
| mst_tx_reset_0 | 1 | O | TX master reset output signal from core to GT of Lane0. |
| mst_rx_reset_0 | 1 | O | RX master reset output signal from core to GT of Lane0. |
| mst_tx_reset_1 | 1 | O | TX master reset output signal from core to GT of Lane1. |
| mst_rx_reset_1 | 1 | O | RX master reset output signal from core to GT of Lane1. |
| mst_tx_reset_2 | 1 | O | TX master reset output signal from core to GT of Lane2. This port is available only if the core speed is 40G orRuntime Switchable option is selected in the Configuration tab. |
| mst_rx_reset_2 | 1 | O | RX master reset output signal from core to GT of Lane2. This port is available only if the core speed is 40G or Runtime Switchable option is selected in the Configuration tab. |
| mst_tx_reset_3 | 1 | O | TX master reset output signal from core to GT of Lane3. This port is available only if the core speed is 40G or Runtime Switchable option is selected in the Configuration tab. |
| mst_rx_reset_3 | 1 | O | RX master reset output signal from core to GT of Lane3. This port is available only if the core speed is 40G or Runtime Switchable option is selected in the Configuration tab. |
| txuserrdy_out_0 | 1 | O | TX user ready output signal from core (reset Interface IP) to GT of Lane0. |
| rxuserrdy_out_0 | 1 | O | RX user ready output signal from core (reset Interface IP) to GT of Lane0. |
| txuserrdy_out_1 | 1 | O | TX user ready output signal from core (reset Interface IP) to GT of Lane1. |
| rxuserrdy_out_1 | 1 | O | RX user ready output signal from core (reset Interface IP) to GT of Lane1. |
| txuserrdy_out_2 | 1 | O | TX user ready output signal from core (reset Interface IP) to GT of
Lane2. This port is available only if the core speed is 40G or Runtime Switchable option is selected in the Configuration tab. |
| rxuserrdy_out_2 | 1 | O | RX user ready output signal from core (reset Interface IP) to GT of
Lane2. This port is available only if the core speed is 40G or Runtime Switchable option is selected in the Configuration tab. |
| txuserrdy_out_3 | 1 | O | TX user ready output signal from Core (reset Interface IP) to GT of
Lane3. This port is available only if the core speed is 40G or Runtime Switchable option is selected in the Configuration tab. |
| rxuserrdy_out_3 | 1 | O | RX user ready output signal from core (Reset Interface IP) to GT of
Lane3. This port is available only if the core speed is 40G or Runtime Switchable option is selected in the Configuration tab. |
| rx_resetdone_out_0 | 1 | O | RX user ready output signal from core to example design. |
| tx_resetdone_out_0 | 1 | O | TX user ready output signal from core to example design. |
| mst_rx_dp_reset_* | 1 | O | RX reset output signal from GT reset IP to the core (Versal devices only). |
| mst_tx_dp_reset_* | 1 | O | TX reset output signal from GT reset IP to the core (Versal devices only). |
| gtm_txdata_in_0 | 255 | O | For GT type equal to GTM, this is the TX data output signal from the core to GT of Lane0. |
| gtm_txdata_in_1 | 255 | O | For GT type equal to GTM, this is the TX data output signal from the core to GT of Lane1. |
| gtm_txdata_in_2 | 255 | O | For GT type equal to GTM, this is TX data output signal from core to GT of Lane2. This port is available only if the core speed is 40G or Runtime Switchable option is selected in the Configuration tab. |
| gtm_txdata_in_3 | 255 | O | For GT type equal to GTM, this is tx data output signal from core to GT of Lane3. This port is available only if the core speed is 40G or Runtime Switchable option is selected in the Configuration tab. |
| gtm_rxdata_out_0 | 255 | I | For GT type equal to GTM, this is RX data input signal from GT to core of Lane0 |
| gtm_rxdata_out_1 | 255 | I | For GT type equal to GTM, this is RX data input signal from GT to core of Lane1 |
| gtm_rxdata_out_2 | 255 | I | For GT type equal to GTM, this is RX data input signal from GT to core of Lane2. This port is available only if the core speed is 40G or Runtime Switchable option is selected in the Configuration tab. |
| gtm_rxdata_out_3 | 255 | I | For GT type equal to GTM, this is RX data input signal from GT to core of Lane3. This port is available only if core speed is 40G or Runtime Switchable option is selected in the Configuration tab. |