The read and write through the AXI4-Lite slave module interface is controlled by a state machine as shown in the following figure:
Figure 1. User State Machine for the AXI4-Lite Interface
A functional description of each state is described as below:
- IDLE_STATE
- By default, the FSM is in IDLE_STATE. When the
user_read_req
signal becomes High, it moves to READ_STATE else ifuser_write_req
signal is High, it moves to WRITE_STATE else it remains in IDLE_STATE. - WRITE_STATE
- You provide
S_AXI_AWVALID
,S_AXI_AWADDR
,S_AXI_WVALID
,S_AXI_WDATA
, andS_AXI_WSTRB
in this state to write to the register map through AXI. WhenS_AXI_BVALID
andS_AXI_BREADY
from AXI slave are High, it moves to ACK_STATE. If any write operation happens in any illegal addresses, theS_AXI_BRESP[1:0]
indicates 2'b10 that asserts the write error signal. - READ_STATE
- You provide
S_AXI_ARVALID
andS_AXI_ARADDR
in this state to read from the register map through AXI. WhenS_AXI_RVALID
andS_AXI_RREADY
are High, it moves to ACK_STATE. If any read operation happens from any illegal addresses, the S_AXI_RRESP[1:0] indicates 2'b10 that asserts the read error signal. - ACK_STATE
- The state moves to IDLE_STATE.