|
Core Specifics |
| Supported Device Family |
Versal™
ACAP |
| Supported User Interfaces |
AXI4, AXI4-Lite, AXI4-Stream, Native, and NoC |
| Provided with
Core
|
| Design Files |
Verilog |
| Example Design |
Refer block automation for
DDR/CPM reference designs |
| Test Bench |
N/A |
| Constraints File |
N/A |
| Simulation Model |
N/A |
| Supported S/W Driver |
N/A |
| Tested Design Flows |
| Design Entry |
Vivado® Design Suite
|
| Simulation |
For supported simulators, see the Xilinx Design Tools: Release Notes
Guide. |
| Synthesis |
Vivado Synthesis |
| Support |
| All Vivado IP Change Logs |
Master Vivado IP Change Logs: 72775
|
|
Xilinx Support web page
|
- For a complete list of supported devices, see the
Vivado®
IP catalog.
- For the supported versions of the tools, see
the Xilinx Design Tools: Release Notes
Guide.
|