Core Overview - 3.0 English

Control Interfaces and Processing System LogiCORE IP Product Guide (PG352)

Document ID
PG352
Release Date
2021-06-16
Version
3.0 English

The Control Interfaces and Processing System IP core instantiates, boots, and configures the processing system section of the Xilinx® Versal™ platform.

CIPS 3.0 is architected as a hierarchical IP encapsulating two sub-IPs namely PS-PMC and CPM IPs. Designing for Versal™ always requires at the least the PMC involvement and therefore CIPS to be configured.