CIPS Presets - 3.0 English

CIPS 3.0 is enabled with default configurations for CIPS parameters referred as Presets. The Presets facilitate design creation and block automation and enable users to quickly configure the IP through GUI without digging into parameter details. Different Presets are available based on the selected Design Flow. The default Presets represent the simplest and necessary options to set up. The options are based on traditional, most encountered use-cases, and on device minimal boot and run-time requirements.

There are two Design Flows available namely PL Subsystem and Full System. On the basis of the Design Flow selected, the default Presets configurations are enabled into selected parameter.

Tip: It allows changing Presets value by user at later stage in PS PMC and CPM windows.

Clicking Apply Configuration in Presets enables user to import presets through Presets Tcl file.

Enabled Presets provides a summary of selected parameters for configuration.

Having Presets in CIPS ensures minimum amount of steps required to achieve the configuration needed for their flow.

PL Subsystem: It stands for PMC + PL where no Processing System is used. It is aimed at traditional FPGA designers, with no to limited interest in the Processing system. This is why some presets are grayed out in PL Subsystem but enabled in Full System Configuration.
Full System: It stands for PS + PMC + CPM + PL and is aimed at the Embedded designer with a definitive interest in PS and/or CPM configuration and interaction with DDR and potential interaction with PL. The advanced user can select the Full System Design Flow and potentially some presets, but can skip the presets. Click the Next button to access the PS PMC and CPM IPs within CIPS to configure them. It is aimed at an advanced user with knowledge above what is expected as standard.

The presets configurations applied are then visible within the PS PMC IP by clicking Next and accessing the detailed settings within the PS PMC Sub-IP.

Note: The Presets set to Custom do not apply any configuration.

The PS-PMC sub-IP exposes all the details and options hidden in the Presets. Presets can be used as a basis to then tune the configuration further. IO Pins allocations and conflicts resolution are easily achieved through one and only one panel. The IO panel which provides a general view of the interfaces currently selected to leverage MIOs and their respective MIO pins layout. Any MIO conflict is highlighted in red.

Figure 1. Presets in CIPS 3.0

The following are the Presets available in CIPS 3.0 module:

Board Interface Configures default boot mode and the default set of peripherals and clocks found on the selected board part when ps pmc fixed io is selected.
Tip: This is only visible when Full System design flow is selected.
Boot Configuration Selects boot configuration from Master, Slave, JTAG, or Custom.
Clock Settings Sets the system reference clock frequency REF_CLK to 33.33 MHz.
Connectivity to MC via NoC Enables the dedicated connectivity that can be used to connect to a NoC instance with a memory controller.
IO Peripherals
Tip: This is not applicable when PL Subsystem is selected in the Design Flow.
As JTAG is always available on Versal, the Debug preset set to custom or JTAG has no effect and defaults to JTAG support via DAP.
Debug Selects one of the debug option from JTAG, HIGH Speed Debug Port (HSDP), or Custom.
Device Integrity Enables you to monitor and respond to the system operating conditions and exceptional events.
PS PL Connectivity Selects Single FPD and Master/Slave LPD clock.
Tip: This is not applicable when PL Subsystem is selected in the Design Flow.