Available Physical Optimizations - 2023.1 English

Vivado Design Suite User Guide: Implementation (UG904)

Document ID
UG904
Release Date
2023-05-16
Version
2023.1 English

The Vivado tools perform the physical optimizations on the in-memory design, as shown in the following table.

Important: Physical optimization can be limited to specific optimizations by choosing the corresponding command options. Only those specified optimizations are run, while all others are disabled, even those normally performed by default.
Table 1. Post-Place and Post-Route Physical Optimizations
Option Name post-place post-route
valid default valid default
Critical Cell Optimization Y 1 Y 1 Y 1 N
Fanout Optimization Y 1 Y 1 N N/A
Very High Fanout Optimization Y 1 Y 1 N N/A
Interconnect Retiming Y 2 Y 2 Y 2 Y 2
Critical Cell Group Optimization Y 2 Y 2 N N/A
Clock Optimization Y 2 Y 2 Y Y
DSP Register Optimization Y Y N N/A
Block RAM Register Optimization Y Y N N/A
URAM Register Optimization Y Y N N/A
Shift Register Optimization Y Y N N/A
Critical Pin Optimization Y Y Y Y
LUT Restructure Optimization Y Y Y Y
Single LUT Optimization Y 2 Y 2 Y 2 Y 2
LUT Cascade Optimization Y 2 Y 2 N N/A
Placement Optimization Y 1 Y 1 Y 1 Y 1
Routing Optimization N N/A Y Y
Block RAM Enable Optimization Y 1 N N N/A
Hold-Fixing Y N Y N
Negative-Edge FF Insertion Y N N N/A
Laguna Hold-Fix Optimization N N/A Y 1 N
Forced Net Replication Y N N N/A
SLR-Crossing Optimization Y 1 Y 1 Y 1 Y 1
  1. For UltraScale only.
  2. For Versal devices only.

When an optimization is performed on a primitive cell, the PHYS_OPT_MODIFIED property of the cell is updated to reflect the optimizations performed on the cell. When multiple optimizations are performed on the same cell, the PHYS_OPT_MODIFIED value contains a list of optimizations in the order they occurred. The following table lists the phys_opt_design options that trigger an update to the PHYS_OPT_MODIFIED property and the corresponding value.

Table 2. Optimization Options and Values
phys_opt_design Option PHYS_OPT_MODIFIED Value
-fanout_opt FANOUT_OPT
-placement_opt PLACEMENT_OPT
-routing_opt MISC_OPT
-slr_crossing_opt SLR_CROSSING_OPT
-insert_negative_edge_ffs INSERT_NEGEDGE
-restruct_opt RESTRUCT_OPT
-interconnect_retime IMR_RETIME_OPT
-lut_opt MISC_OPT
-casc_opt MISC_OPT
-cell_group_opt CELL_GROUP_OPT
-critical_cell_opt CRITICAL_CELL_OPT
-dsp_register_opt DSP_REGISTER_OPT
-bram_register_opt BRAM_REGISTER_OPT
-uram_register_opt URAM_REGISTER_OPT
-shift_register_opt SHIFT_REGISTER_OPT
-hold_fix HOLD_FIX
-aggressive_hold_fix HOLD_FIX
-retime MISC_OPT
-force_replication_on_nets FORCE_REPLICATION_ON_NETS
-critical_pin_opt MISC_OPT
-clock_opt CLOCK_OPT
-sll_reg_hold_fix MISC_OPT