Port Mapping and Supported Port Types

Port Mapping and Supported Port Types - 2023.1 English

Vivado Design Suite User Guide: Logic Simulation (UG900)

Document ID

UG900

Release Date

2023-05-16

Version

2023.1 English

The following table lists the supported port types.

Table 1. Supported Port Types
VHDL¹	Verilog/SV ²
IN	INPUT
OUT	OUTPUT
INOUT	INOUT
Buffer and linkage ports of VHDL are not supported. Connection to bi-directional pass switches in Verilog are not supported. Unnamed Verilog ports are not allowed on mixed design boundary.

The following table shows the supported VHDL and Verilog data types for ports on the mixed language design boundary.

Table 2. Supported VHDL and Verilog Data Types
VHDL Port	Verilog Port
`bit`	net
`std_logic`	net
`bit_vector`	vector net
`signed`	vector net
`unsigned`	vector net
`std_ulogic_vector`	vector net
`std_logic_vector`	vector net

Note: Verilog output port of type reg is supported on the mixed language boundary. On the boundary, an output reg port is treated as if it were an output net (wire) port. Any other type found on mixed language boundary is considered an error.

Note: The Vivado simulator supports the record element as an actual in the port map of a Verilog module that is instantiated in the mixed domain. All those types that are supported as VHDL port (listed in Table 2) are also supported as a record element.

Table 3. Supported SV and VHDL Data Types
SV Data type	VHDL Data type
Int
	`bit_vector`
	`std_logic_Vector`
	`std_ulogic_vector`
	`signed`
	`unsigned`
byte
	`bit_vector`
	`std_logic_Vector`
	`std_ulogic_vector`
	`signed`
	`unsigned`
shortint
	`bit_vector`
	`std_logic_Vector`
	`std_ulogic_vector`
	`signed`
	`unsigned`
longint
	`bit_vector`
	`std_logic_Vector`
	`std_ulogic_vector`
	`signed`
	`unsigned`
integer
	`bit_vector`
	`std_logic_Vector`
	`std_ulogic_vector`
	`signed`
	`unsigned`
vector of bit(1D)
	`bit_vector`
	`std_logic_Vector`
	`std_ulogic_vector`
	`signed`
	`unsigned`
vector of logic(1D)
	`bit_vector`
	`std_logic_Vector`
	`std_ulogic_vector`
	`signed`
	`unsigned`
vector of reg(1D)
	`bit_vector`
	`std_logic_Vector`
	`std_ulogic_vector`
	`signed`
	`unsigned`
logic/bit
	`bit`
	`std_logic`
	`std_ulogic`
	`bit_vector`
	`std_logic_Vector`
	`std_ulogic_vector`
	`signed`
	`unsigned`

Note: VHDL entity instantiating Verilog Module having real port is supported.