Generics (Parameters) Mapping - 2023.1 English

Vivado Design Suite User Guide: Logic Simulation (UG900)

Document ID
UG900
Release Date
2023-05-16
Version
2023.1 English

The Vivado simulator supports the following VHDL generic types (and their Verilog/SV equivalents):

  • integer
  • real
  • string
  • boolean
    Note: Any other generic type found on mixed language boundary is considered an error.