IEEE std_logic Type - 2023.1 English

Vivado Design Suite User Guide: Logic Simulation (UG900)

Document ID
UG900
Release Date
2023-05-16
Version
2023.1 English

A single bit of VHDL std_logic and std_ulogic is represented in C/C++ as a single byte (char or unsigned char). The following table shows the values of std_logic/std_ulogic and their C/C++ equivalents.

Table 1. std_logic/std_ulogic Values and their C/C++ Equivalents
std_logic Value C/C++ Byte Value (Decimal)
'U‘ 0
‘X‘ 1
‘0‘ 2
‘1‘ 3
‘Z‘ 4
‘W‘ 5
‘L‘ 6
‘H‘ 7
‘_‘ 8

Example code:

// Put a '1' on signal "clk," where "clk" is defined as
// signal clk : std_logic;
const char one_val = 3; // C encoding for std_logic '1'...
int clk = loader.get_port_number("clk");
loader.put_value(clk, &one_val); // set clk to 1