Data Types Allowed on the Boundary of C and SystemVerilog - 2023.1 English

Vivado Design Suite User Guide: Logic Simulation (UG900)
Document ID
UG900
Release Date
2023-05-16
Version
2023.1 English
The IEEE Standard for SystemVerilog allows only subsets of C and SystemVerilog data types on the C and SystemVerilog boundary. Provided below are:
  1. Details on data types supported in Vivado simulator.
  2. Descriptions of mapping between the C and SystemVerilog data types.