Step 3: Creating External Connections - 2022.1 English

Vivado Design Suite Tutorial: Designing IP Subsystems Using IP Integrator (UG995)

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2022.1 English
At this point, you have instantiated several AXI slaves that you can access through an external master such as an on-board processor. To connect to an external master controlling these slaves, you will connect the S00_AXI interface pin on the AXI Interconnect to an external port.

An interface is a grouping of signals that share a common function, containing both individual signals and multiple buses. By grouping these signals and buses into an interface, the Vivado IP integrator can identify common interfaces and automatically make multiple connections in a single step. See the Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994) for more information on interface pins and ports.

  1. Right-click the S00_AXI interface pin on the AXI Interconnect to open the popup menu and select Create Interface Port.

    The Create Interface Port dialog box opens, as shown in the following figure.

  2. Click OK to accept the default settings.

    The Vivado IP integrator adds the external S00_AXI interface port to the subsystem design, and automatically connects it to the S00_AXI interface pin on the AXI Interconnect core.

    On the AXI Interconnect, connect the Clock and the Reset pin to external ports using the Create Port command. Because these are not interface pins, you will not need an interface port to connect them.

  3. Right-click the ACLK pin of the AXI Interconnect, and select Create Port, as shown in the following figure:

  4. In the Create Port dialog box, as shown in the following figure, for Frequency (MHz), enter 200, and leave the remaining fields set to the default values.
  5. Click OK.

  6. Right-click the ARESETN pin of the AXI Interconnect, and select Create Port.

    The Create Port dialog box opens as seen in the following figure.

  7. For Polarity, select Active Low.
  8. Click OK.

    Important: IP integrator treats an external reset coming into the block design as asynchronous to the clocks. You should always synchronize the external resets with a clock domain in the IP subsystem to help the design meet timing.

    You can use a Processor System Reset block (proc_sys_reset) to synchronize the reset. The Processing System Reset is a soft IP that handles numerous reset conditions at its input and generates appropriate system reset signals at its output; however, if a clock and a reset are external inputs to the block design, and the reset signal synchronizes externally to the clock, then you need to associate the related clock with the reset. This does not require the Processor System Reset block.

  9. Double-click the ACLK port to open the Customize Port dialog box.
  10. A clock is typically associated with a Bus Interface. In this case, you can associate this clock pin to the S00_AXI interface. In the Associated Busif field, type S00_AXI.
  11. For the Associated Reset field, enter ARESETN.
  12. Click OK.

    The dialog box looks like the following figure:

    Now you can connect the AXI clock and reset nets to the remaining master and slave clocks and resets of the AXI Interconnect.

  13. Place the cursor on top of the S00_ACLK pin of the AXI Interconnect.
    Note: The cursor changes into a pencil indicating that a connection can be made from that pin. Clicking the mouse button here starts a connection on the S00_ACLK pin.
  14. Click and drag the cursor from the S00_ACLK pin to the ACLK port.
    Tip: You must press and hold down the mouse button while dragging the connection from the S00_ACLK pin to the ACLK port.

    As you drag the connection wire, a green checkmark appears on the ACLK port indicating that you can make a valid connection between these points. The Vivado IP integrator highlights all possible connection points in the subsystem design as you interactively wire the pins and ports.

  15. Release the mouse button and Vivado IP integrator makes a connection between the S00_ACLK pin and the ACLK port, as shown in the following figure:

  16. Repeating the steps outlined above, connect the M00_ACLK and the M01_ACLK to the ACLK port.
    The connections to the AXI Interconnect should now appear as shown in the following figure:

    Similarly, connect the reset pins of all the masters and slaves to the ARESETN port.

  17. Place the cursor on the S00_ARESETN pin, then click and drag the cursor to the ARESETN port, as shown below.
  18. Release the mouse button to make the connection.

  19. Repeat the steps to connect the M00_ARESETN and the M01_ARESETN pins of the AXI Interconnect to the ARESETN port, as shown in the following figure: