Introduction - 2022.1 English

Vivado Design Suite Tutorial: Designing IP Subsystems Using IP Integrator (UG995)

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Release Date
2022.1 English
Important: This tutorial requires the use of the Kintex®-7 family of devices. You will need to update your Vivado® tools installation if you do not have this device family installed. Refer to the Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973) for more information on Adding Design Tools or Devices.

The Xilinx® Vivado® Design Suite IP integrator lets you create complex system designs by instantiating and interconnecting IP cores from the Vivado IP catalog onto a design canvas. You can create designs interactively through the IP integrator design canvas GUI, or programmatically using a Tcl programming interface. You will typically construct designs at the AXI-interface level for greater productivity; but you may also manipulate designs at the port level for more precise design control.

This tutorial walks you through the steps for building a basic IP subsystem design using the IP integrator. You will instantiate a few IP in the IP integrator and then stitch them up to create an IP subsystem design. While working through this tutorial, you will be introduced to the IP integrator GUI, run design rule checks (DRC) on your design, and then integrate the design into a top-level design in the Vivado Design Suite. Finally, you will run synthesis and implementation and generate a bitstream on the design.

Video: You can also view the Designing with Vivado IP Integrator quick take video to learn more about this feature of the Vivado Design Suite.